器件名称: CS18LV20483AFI-70
功能描述: High Speec Super Low Power SRAM
文件大小: 757.5KB 共16页
简 介:High Speed Super Low Power SRAM
256K-Word By 8 Bit
CS18LV20483
Revision History
Rev. No. 1.0
History Initial issue
Issue Date Jan.26,2005
Remark
1
Rev. 1.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
256K-Word By 8 Bit
CS18LV20483
GENERAL DESCRIPTION
The CS18LV20483 is a high performance, high speed, and super low power CMOS Static Random Access Memory organized as 262,144 words by 8 bits and operates from a wide range of 2.7 to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.50uA and maximum access time of 55/70ns in 3.0V operation. Easy memory expansion is provided by an active LOW chip enable inputs (/CE1,CE2) and active LOW output enable (/OE) and three-state output drivers. The CS18LV20483 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The CS18LV20483 is available in JEDEC standard 32-pin sTSOP (8x13.4 mm), TSOP (8x20mm), TSOP (II) (400mil) and SOP (450 mil) packages.
.
FEATURES
Low operation voltage : 2.7 ~ 3.6V Ultra low power consumption : 2mA＠1MHz (Max.) operating current 0.50 uA (Typ.) CMOS standby current High speed access time : 55/70ns (Max.) at Vcc = 3.0V. Automatic power down when chip is deselected. Three state outputs and TTL compatible Data retention supply voltage as low as 1.5V. Easy expansion with /CE and /OE ……
