用8位微处理器实现数字低通滤波器设计
滤波常发生在模拟世界。不幸的是，在数字领域，工程师通常主要使用DSP（数字信号处理器），而不是8位单片机实现滤波。这个情形的发生，是因为滤波器设计的算法比大多数工程师乐于处理的算法更复杂。而且，数字滤波需要计算整形数，而不是浮点数。这引发了两个问题。第一，有限位的舍入误差降低了滤波器响应，甚至使它不稳定。第二，必须用整数算法处理小数值。
有几种方法解决这些问题。例如，可以使用16、32和64位数的操作，或可以缩放到更好的精度。这些和其他方法通常需要更多的存储器，造成编程经常不适于小型微处理器。文献研究所示用C语言编写的数字滤波固件，与用汇编语言编写需要更多的存储器。这个情形对存储器资源有限的小型微处理器来讲，常常是不可接受的。
列表1（程序见英文原文）列出了一个用8位微处理器设计单极低通数字滤波器固件的简单方法。Freescale公司的低端MC68HC908QT2使用汇编编程器，但可以将本设计方案用于任一型号微处理器，只要其使用的也是标准汇编指令。
将基于广义Z
变换算法的复杂设计方案放在一边，本方案使用了一种基于递归方程的解决办法。计算每个输出信号采样，作为输入信号和前一个输出信号带相关系数的总和。递归方程定义一个单极低通滤波器为：Y[n]=X[n]×a0+Y[n–1]×b1，在这里X[n]和Y[n]为采样[n]的输入输出值，Y[n–1]为前一采样[n–1]的输出值，a0和b1为减少δ控制的权重系数。系数为0δ1的值，a0=1–δ且b1=δ。理论上，δ为输入信号从高电平降到低电平时，邻近的输出采样之间的衰减量。可以直接指定δ值或找到滤波器所需的时间常数d，其为采样数上升到低通滤波器稳态63.2%时的输出。D和δ之间存在确定的关系：δ=e–1/d，在这里e为自然对数基底。前面的公式服从Y[n]=Y[n–1]+(1–δ)×(X[n]–Y[n–1])。
为取代小数相乘，1–δ对汇编程序而言，用除以倒数为整数的方法更方便，F=1/(1–δ): Y[n]=Y[n–1]+(X[n]–Y[n–1])/F。因此，可以按照下面的步骤确定数字滤波器参数：
1、选择参数F。对汇编程序而言，便于用右移实现除法运算。右移就是F值应该为2S，在此S为偏移数。让F为8，相当于右移三位。
2、计算衰减：δ=1–1/F=1–1/8=0.875。
3、计算时间常数d=–1/lnδ=–1/ln0.875=7.49采样。
公式Y[n]=Y[n–1]+(X[n]–Y[n–1])/F决定滤波器的微处理器算法设计。算法需要三个寄存器：输入X[n]、输出Y[n]和一个递增寄存器保存(X[n]–Y[n–1])/F的值。三个寄存器的大小取决于输入。应用中，内置的8位ADC输出范围从00到$FF的信号，必须经历低通滤波器。所以输入和输出寄存器均为1个字节。为增加除法精度，增加一半除数到被除数。这个处理将递增寄存器增加到2个字节。
用数字方法实现滤波功能提供了一致性的好处，因为器件误差、温度漂移和老化不会影响滤波器算法。用微处理器实现数字滤波器，增加了可调整滤波器参数的灵活性优势，因为这个灵活性仅取决于固件。
英文原文：
8-bit microcontroller implements digital lowpass filter
A simple assembler routine fits a digital lowpass filter into a microcontroller.
Abel Raynus, Armatron International, Malden, MA; Edited by Charles H Small and Fran Granville -- EDN, 1/24/2008
Filtering occurs frequently in the analog world. Unfortunately, in the digital world, engineers apply it mainly to the DSPs (digital-signal processors) and not to the small 8-bit microcontrollers that designers commonly use. This situation occurs because the math for the filter design is more complicated than most engineers are willing to deal with. Moreover, digital filtering requires calculations on integers instead of on floating-point numbers. This scenario causes two problems. First, the rounding-off error from the limited number of bits can degrade the filter response or even make it unstable. Second, you must handle the fractional values with integer math.
Several ways exist to solve these issues. For example, you can use operations with 16-, 32-, and 64-bit numbers, or you can scale for better accuracy. These and other methods usually require more memory, and, as a result, the program often does not fit into a small microcontroller. A literature search shows that published digital-filter firmware is written in C. Programs in C need more memory than those written in assembler. This situation often makes them unacceptable for small microcontrollers with limited memory resources.
Listing 1 shows a simple engineering method to design single-pole, lowpass-digital-filter firmware for 8-bit microcontrollers. The low-end Freescale MC68HC908QT2 is the target of the assembler program, but you can apply this Design Idea to any type of microcontroller because it uses only standard assembler instructions.
Leaving aside the sophisticated design methods based on Z transformation with its extensive math, this idea uses another approach based on a recursive equation. You calculate each output-signal sample as the sum of the input signal and the previous output signal with corresponding coefficients. A recursive equation defines a single-pole lowpass filter as: Y[n]=X[n]×a0+Y[n–1]×b1, where X[n] and Y[n] are input and output values of sample [n], Y[n–1] is an output value of the previous sample [n–1], and a0 and b1 are weight coefficients that decrement δ controls. The coefficients have the value of 0δ1, a0=1–δ, and b1=δ. Physically, δ is the amount of decay between adjacent output samples when the input signal drops from a high level to a low level. You can directly specify the value of δ or find it from the desired time constant of the filter, d, which is the number of samples it takes the output to rise to 63.2% of the steady-state level for a lowpass filter. A fixed relationship exists between d and δ: δ=e–1/d, where e is the base of natural logarithms. The preceding equations yield Y[n]=Y[n–1]+(1–δ)×(X[n]–Y[n–1]).
Instead of multiplying a decimal-point number, 1–δ, it is more convenient for assembler programming to divide by the reciprocal integer, F=1/(1–δ): Y[n]=Y[n–1]+(
X[n]–Y[n–1])/F. Thus, you can determine the digital filter’s parameters using the following steps:
Choose the parameter F. For assembler, it is convenient to perform division as right shifts. For right shifts, the value of F should be 2S, where S is the number of shifts. Let F equal 8, which you reach after three right shifts.
Calculate the decrement: δ=1–1/F=1–1/8=0.875.
Calculate the time constant as d=–1/lnδ=–1/ln0.875=7.49 samples.
The equation Y[n]=Y[n–1]+(X[n]–Y[n–1])/F determines the design of the microcontroller’s algorithm for the filter. The algorithm needs three registers: input for X[n], output for Y[n], and an increment register to keep the (X[n]–Y[n–1])/F term. The size of these registers depends on the inputs. In this application, the signals from the built-in 8-bit ADC range from 00 to $FF and must go through the lowpass filter. So, the input and the output registers are 1 byte in size. To increase the accuracy of division, add half the divisor to the dividend. This action increases the increment register to 2 bytes.
Numerically performing the filtering function provides the benefit of consistency because component tolerances, temperature drift, and aging do not affect the filter’s algorithm. The implementation of the digital filter in the microcontroller gives the additional benefit of flexibility to adjust the filter’s parameters, because this flexibility depends only on the firmware.
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